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for more information, please visit the product page. ????????? ?????????????????? cui .com date 12/21/2015 page 1 of 32 series: ndm2z-25 description: auto compensated, digital dc-dc pol converter model input voltage output voltage output current output wattage (vdc) (vdc) max (a) max (w) ndm2z-25 4.5~14 0.6~3.3 25 82.5 part number key example part number: ndm2z-25v-a-001 vertical module 4.0 mm pin length rmware con guration 001 features ? pin and function compatible with architects of modern power? product standards ? compact package, horizontal: 25.7 x 13.8 x 8.2 mm ? compact package, vertical: 26.3 x 7.6 x 15.60 mm ? 25 a output ? high efficiency ? auto compensation ? smbus interface ? pmbus? compatible general characteristics ? 4.5~14 v input range ? 0.6~3.3 v programmable output ? voltage tracking ? voltage margining ? active current sharing ? snapshot ? parametric capture ? voltage/current/temperature monitoring ? synchronization and phase spreading ? remote differential voltage sense ? programmable soft start and soft stop ? fault management ndm2z-25 x - x - xxx firmware con guration: 000~zzz base number module orientation and pin style: hs = horizontal, surface mount ht = horizontal, through hole mount v = vertical pin con guration: a = both functions present, 4.0 mm pin length (v) b = both functions present, 5.5 mm pin length (v) p = power good (h) v = voltage track (h) * hs and ht modules are delivered on tape and reel * v modules are delivered in trays
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 2 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter absolute maximum ratings parameter conditions/description min typ max units operating temperature (see thermal consideration section) (t p1 ) -40 125 c storage temperature (t s ) -40 125 c input voltage (see operating in- formation section for input and output voltage relations)(v i ) -0.3 16 v logic i/o voltage ctrl, sa0, sa1, salert, scl, sda, vset, sync, ddc, pg -0.3 6.5 v ground voltage differential -s, pref, gnd -0.3 0.3 v analog pin voltage v o , +s, vtrk -0.3 6.5 v notes: stress in excess of absolute maximum ratings may cause permanent damage. absolute maximum ratings, sometimes referred to as no destruction limits, are normally tested with one parameter at a time exceeding the limits in the electrical speci cation. if exposed to stress above these limits, function and performance may degrade in an unspeci ed manner. con? guration file this product is designed with a digital control circuit. the control circuit uses a con guration le which determines the functionality and performance of the product. the electrical speci cation table shows parameter values of functionality and performance with the default con guration le, unless otherwise speci ed. the default con guration le is designed to t most application needs with focus on high ef ciency. if different characteristics are required it is possible to change the con guration le to optimize certain performance characteristics. note that current sharing operation requires changed con guration le. product electrical specification, horizontal t p1 = -30 to +95 c, v i = 4.5 to 14 v, v i > v o + 1.0 v typical values given at: t p1 = +25 c, v i = 12.0 v, max i o , unless otherwise speci ed under conditions. external c in = 470 f/10 m , c out = 470 f/10 m . see operating information section for selection of capacitor types. sense pins are connected to the output pins. parameter conditions/description min typ max units input voltage rise time (v i ) monotonic 2.4 v/ms output voltage without pin-strap (v o ) 1.2 v output voltage adjustment range (v o ) 0.60 3.3 v output voltage adjustment including margining (v o ) see note 17 0.54 3.63 v output voltage set-point resolution (v o ) 0.025 %fs output voltage accuracy (v o ) including line, load, temp see note 14 -1 1 % current sharing operation see note 15 -2 2 % internal resistance +s/-s to vout/gnd (v o ) 47 line regulation (v o ) v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 2 2 2 3 mv mv mv mv load regulation (v o ) i o = 0~100% v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 2 2 2 3 mv mv mv mv output ripple & noise (v oac ) c o = 470 f (minimum external capacitance) see note 11 v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 20 30 40 60 mvp-p mvp-p mvp-p mvp-p
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 3 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter product electrical specification, horizontal ( continued ) parameter conditions/description min typ max units output current (i o ) 025a static input current at max i o (i s ) v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 1.58 2.43 4.13 7.32 a a a a current limit threshold (i lim ) 27 37.5 a short circuit current(i sc ) rms, hiccup mode, see note 3 v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 8 6 5 4 a a a a ef ciency ( ) 50% of max i o v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 84.4 89.4 93.1 95.2 % % % % max i o v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 79.2 85.7 90.8 93.9 % % % % power dissipation at max i o (p d ) v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 3.93 4.17 4.55 5.34 w w w w input idling power (no load)(p li ) default con guration: continues conduction mode, ccm v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 0.56 0.57 0.67 0.92 w w w w input standby power (p ctrl ) turned off with ctrl-pin default con guration: monitoring enabled, precise timing enabled 170 mw internal input capacitance (c i ) 70 f internal output capacitance (c o ) 200 f total external output capacitance (c out ) see note 9 300 15,000 f esr range of capacitors (per single capacitor) (c out ) see note 9 5 30 m load transient peak voltage deviation (l to h/h to l) load step 25-75-25% of max i o (v tr1 ) default con guration di/dt = 2 a/ s c o = 470 f (minimum external capacitance) see note 12 v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 95 105 115 168 mv mv mv mv load transient recovery time note 5 (l to h/h to l) load step 25-75-25% of max i o (t tr1 ) default con guration di/dt = 2 a/ s c o = 470 f (minimum external capacitance) see note 12 v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 74 85 122 140 s s s s switching frequency (f s ) 320 khz switching frequency range (f s ) pmbus con gurable 200-640 khz switching frequency set-point accuracy (f s ) -5 5 % control circuit pwm duty cycle 5 95 % minimum sync pulse width 150 ns input clock frequency drift tolerance external clock source -13 13 %
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 4 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter product electrical specification, horizontal ( continued ) parameter conditions/description min typ max units input under voltage lockout, uvlo uvlo threshold 3.85 v uvlo threshold range pmbus con gurable 3.85-14 v set point accuracy -150 150 mv uvlo hysteresis 0.35 v uvlo hysteresis range pmbus con gurable 0-10.15 v delay 2.5 s fault response see note 3 automatic restart, 70 ms input over voltage protection, iovp iovp threshold 16 v iovp threshold range pmbus con gurable 4.2-16 v set point accuracy -150 150 mv iovp hysteresis 1 v iovp hysteresis range pmbus con gurable 0-11.8 v delay 2.5 s fault response see note 3 automatic restart, 70 ms power good, pg, see note 2 pg threshold 90 %v o pg hysteresis 5 %v o pg delay direct after dlc ms pg delay range pmbus con gurable 0-500 s output voltage over/under voltage protection, ovp/uvp uvp threshold 85 %v o uvp threshold range pmbus con gurable 0-100 %v o uvp hysteresis 5 %v o ovp threshold 115 %v o ovp threshold range pmbus con gurable 100-115 %v o uvp/ovp response time 25 s uvp/ovp response time range pmbus con gurable 5-60 s fault response see note 3 automatic restart, 70 ms over current protection, ocp ocp threshold 32 a ocp threshold range pmbus con gurable 0-32 a protection delay see note 4 32 t sw protection delay range pmbus con gurable 1-32 t sw fault response see note 3 automatic restart, 70 ms over temperature protection, otp at p2 see note 8 otp threshold 120 c otp threshold range pmbus con gurable -40 125 c otp hysteresis 25 c otp hysteresis range pmbus con gurable 0-165 c fault response see note 3 automatic restart, 240 ms
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 5 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter product electrical specification, horizontal ( continued ) parameter conditions/description min typ max units logic input low threshold(v il ) sync, sa0, sa1, scl, sda, ddc, ctrl, vset 0.8 v logic input high threshold (v ih )2v logic input low sink current(i il ) ctrl 0.6 ma logic output low signal level (v ol ) sync, scl, sda, salert, ddc, pg 0.4 v logic output high signal level (v oh ) 2.25 v logic output low sink current (i ol ) 4ma logic output high source current (i oh ) 2ma setup time, smbus(t set ) see note 1 300 ns hold time, smbus(t hold ) see note 1 250 ns bus free time, smbus(t free ) see note 1 2 ms internal capacitance on logic pins (c p ) 10 pf initialization time see note 10 40 ms output voltage delay time see note 6 delay duration see note 16 10 ms delay duration range pmbus con gurable 5-500,000 ms delay accuracy turn-on -0.25/+4 ms delay accuracy turn-off -0.25/+4 ms output voltage ramp time see note 13 ramp duration 10 ms ramp duration range pmbus con gurable 0-200 ms ramp time accuracy 100 s current sharing operation 20 % vtrk input bias current v vtrk = 5.5 v 110 200 a vtrk tracking ramp accuracy (v o - v vtrk ) 100% tracking, see note 7 -100 100 mv current sharing operation 2 phases, 100% tracking v o = 1.0 v, 10 ms ramp 100 mv vtrk regulation accuracy (v o - v vtrk ) 100% tracking -1 1 % current sharing operation 100% tracking -2 2 % current difference between products in a current sharing group steady state operation max 2 x read_iout monitoring accuracy ramp-up 2 a number of products in a current sharing group 7 monitoring accuracy read_vin vs v i 3% read_vout vs v o 1% read_iout vs i o i o = 0-20 a, t p1 = 0 to +95 c v i = 4.5-14 v, v o = 1.0 v 1.7 a read_iout vs i o i o = 0-20 a, t p1 = 0 to +95 c v i = 4.5-14 v, v o = 0.6-3.3 v 3 a
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 6 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter product electrical specification, horizontal ( continued ) notes: 1: see section i 2 c/smbus setup and hold times ? de nitions. 2: monitorable over pmbus interface. 3: automatic restart ~70 or 240 ms after fault if the fault is no longer present. continuous restart attempts if the fault reappear after restart. 4: t sw is the switching period. 5: within +/-3% of vo 6: see section soft-start power up. 7: tracking functionality is designed to follow a vtrk signal with slew rate < 2.4 v/ms. for faster vtrk signa ls accuracy will depend on the regulator bandwidth. 8: see section over temperature protection (otp). 9: see section external capacitors. 10: see section initialization procedure. 11: see graph output ripple vs external capacitance and operating information section output ripple and noise. 12: see graph load transient vs. external capacitance and operating information section external capacitors. 13: time for reaching 100% of nominal vout. 14: for vout < 1.0 v accuracy is +/-10 mv. for further deviations see section output voltage adjust using pmbus. 15: accuracy here means deviation from ideal output voltage level given by con gured droop and actual load. includes line, load and temperature variations. 16: for current sharing the output voltage delay time must be recon gured to minimum 15 ms. 17: for steady state operation above 1.05 x 3.3 v, please contact your local cui sales representative.
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 7 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter efficiency vs. output current, v i = 5 v power dissipation vs. output current, v i = 5 v efficiency vs. load current and output voltage: t p1 = +25 c, v i = 5 v, f sw = 320 khz, c o = 470 f/10 m. dissipated power vs. load current and output voltage: t p1 = +25 c, v i = 5 v, f sw = 320 khz, c o = 470 f/10 m. efficiency vs. output current, v i = 12 v power dissipation vs. output current, v i = 12 v efficiency vs. load current and output voltage at t p1 = +25 c, v i = 12 v, f sw = 320 khz, c o = 470 f/10 m. dissipated power vs. load current and output voltage: t p1 = +25 c, v i = 12 v, f sw = 320 khz, c o = 470 f/10 m. efficiency vs. output current and switching frequency power dissipation vs. output current and switching frequency efficiency vs. load current and switch frequency at t p1 = +25 c, v i = 12 v, v o = 1.0 v, c o = 470 f/10 m. default configuration except changed frequency dissipated power vs. load current and switch frequency at t p1 = +25 c, v i = 12 v, v o = 1.0 v, c o = 470 f/10 m. default configuration except changed frequency 75 80 85 90 95 100 0 5 10 15 20 25 [%] [a] 0.6 v 1.0 v 1.8 v 3.3 v 0 1 2 3 4 5 6 0 5 10 15 20 25 [w] [a] 0.6 v 1.0 v 1.8 v 3.3 v 75 80 85 90 95 100 0 5 10 15 20 25 [%] [a] 0.6 v 1.0 v 1.8 v 3.3 v 0 1 2 3 4 5 6 0 5 10 15 20 25 [w] [a] 0.6 v 1.0 v 1.8 v 3.3 v 70 75 80 85 90 95 0 5 10 15 20 25 [%] [ a ] 200 khz 320 khz 480 khz 640 khz 0 1 2 3 4 5 6 0 5 10 15 20 25 [w] [ a ] 200 khz 320 khz 480 khz 640 khz typical characteristics, horizontal ( continued )
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 8 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter load transient vs. external capacitance, v o = 1.0 v load transient vs. external capacitance, v o = 3.3 v load transient peak voltage deviation vs. external capacitance. step (6.25-18.75-6.25 a). parallel coupling of capacitors with 470 f/10 m, t p1 = +25 c, v i = 12 v, v o = 1.0 v, f sw = 320 khz, di/dt = 2 a/s load transient peak voltage deviation vs. external capacitance. step (6.25-18.75-6.25 a). parallel coupling of capacitors with 470 f/10 m, t p1 = +25 c, v i = 12 v, v o = 3.3 v, f sw = 320 khz, di/dt = 2 a/s load transient vs. switch frequency load transient peak voltage deviation vs. frequency. step-change (6.25-18.75-6.25 a). t p1 = +25 c. v i = 12 v, v o = 1.0 v, c o = 470 f/10 m note: for universal pid, see section dynamic loop compensation (dlc). 0 100 200 300 400 012345 [mv] [mf] universal pid, no nlr dlc, no nlr universal pid, default nlr dlc, default nlr universal pid, opt. nlr dlc, opt. nlr 0 100 200 300 400 012345 [mv] [mf] universal pid, no nlr dlc, no nlr universal pid, default nlr dlc, default nlr universal pid, opt. nlr dlc, opt. nlr 0 100 200 300 400 200 300 400 500 600 [mv] [khz] universal pid, no nlr dlc, no nlr universal pid, default nlr dlc, default nlr universal pid, opt. nlr dlc, opt. nlr typical characteristics, horizontal ( continued )
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 9 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter output current derating, v o = 0.6 v output current derating, v o = 1.0 v a vailable load current vs. ambient air temperature and airflow at v o = 0.6 v, v i = 12 v. see thermal consideration section. available load current vs. ambient air temperature and airflow at v o = 1.0 v, v i = 12 v. see thermal consideration section. output current derating, v o = 1.8 v output current derating, v o = 3.3 v a vailable load current vs. ambient air temperature and airflow at v o = 1.8 v, v i = 12 v. see thermal consideration section. a vailable load current vs. ambient air temperature and airflow at v o = 3.3 v, v i = 12 v. see thermal consideration section. current limit characteristics, v o = 1.0 v current limit characteristics, v o = 3.3 v o utput voltage vs. load current at t p1 = +25 c, v o = 1.0 v. note: output enters hiccup mode at current limit. o utput voltage vs. load current at t p1 = +25 c, v o = 3.3 v. note: output enters hiccup mode at current limit. 0 5 10 15 20 25 30 60 70 80 90 100 110 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0 5 10 15 20 25 30 60 70 80 90 100 110 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0 5 10 15 20 25 30 50 60 70 80 90 100 110 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0 5 10 15 20 25 30 50 60 70 80 90 100 110 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0,0 0,2 0,4 0,6 0,8 1,0 1,2 25 27 29 31 33 35 [v] [a] 4.5 v 5.0 v 12 v 14 v v i = 4.5 v v i = 5.0, 12, 14 v 0,0 1,0 2,0 3,0 4,0 25 27 29 31 33 35 [v] [a] 4.5 v 5.0 v 12 v 14 v v i = 4.5, 5.0 v v i = 12, 14 v typical characteristics, horizontal ( continued )
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 10 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter output ripple vs. input voltage output ripple vs. frequency output voltage ripple v pk-pk at: t p1 = +25 c, c o = 470 f/10 m, i o = 25 a output voltage ripple v pk-pk at: t p1 = +25 c, v i = 12 v , c o = 470 f/10 m, i o = 25 a. default configuration except changed frequency. output ripple vs. external ca pacitance load regulation, v o = 1.0 v output voltage ripple v pk-pk at: t p1 = +25 c, v i = 12 v. i o = 25 a. parallel coupling of capacitors with 470 f/10 m load regulation at v o = 1.0 v, t p1 = +25 c, c o = 470 f/10 m 0 10 20 30 40 50 60 70 5791113 [mv pk-pk ] [v] 0.6 v 1.0 v 1.8 v 3.3 v 0 30 60 90 120 150 200 300 400 500 600 [mv pk-pk ] [khz] 0.6 v 1.0 v 1.8 v 3.3 v 0 10 20 30 40 50 60 70 012345 [mv] [mf] 0.6v 1.0 v 1.8 v 3.3 v 0,990 0,995 1,000 1,005 1,010 0 5 10 15 20 25 [v] [a] 4.5 v 5.0 v 12 v 14 v typical characteristics, horizontal ( continued )
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 11 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter start-up by input source shut-down by input source start-up enabled by connecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 25 a top trace: output voltage (0.5 v/div.). bottom trace: input voltage (5 v/div.). time scale: (20 ms/div.). shut-down enabled by disconnecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 25 a top trace: output voltage (0.5 v/div.). bottom trace: input voltage (5 v/div.). time scale: (2 ms/div.). start-up by ctrl signal shut-down by ctrl signal start-up by enabling ctrl signal at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 25 a top trace: output voltage (0.5 v/div.). bottom trace: ctrl signal (2 v/div.). time scale: (20 ms/div.). shut-down enabled by disconnecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 25 a top trace: output voltage (0.5 v/div). bottom trace: ctrl signal (2 v/div.). time scale: (2 ms/div.). typical characteristics, horizontal ( continued )
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 12 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter product electrical specification, vertical t p1 = -30 to +95 c, v i = 4.5 to 14 v, v i > v o + 1.0 v typical values given at: t p1 = +25 c, v i = 12.0 v, max i o , unless otherwise speci ed under conditions. external c in = 470 f/10 m , c out = 470 f/10 m . see operating information section for selection of capacitor types. sense pins are connected to the output pins. parameter conditions/description min typ max units input voltage rise time (v i ) monotonic 2.4 v/ms output voltage without pin-strap (v o ) 1.2 v output voltage adjustment range (v o ) 0.60 3.3 v output voltage adjustment including margining (v o ) see note 17 0.54 3.63 v output voltage set-point resolution (v o ) 0.025 %fs output voltage accuracy (v o ) including line, load, temp see note 14 -1 1 % current sharing operation see note 15 -2 2 % internal resistance +s/-s to vout/gnd (v o ) 47 line regulation (v o ) v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 2 2 2 3 mv mv mv mv load regulation (v o ) i o = 0~100% v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 2 2 2 3 mv mv mv mv output ripple & noise (v oac ) c o = 470 f (minimum external capacitance) see note 11 v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 20 30 40 60 mvp-p mvp-p mvp-p mvp-p output current (i o ) 020a static input current at max i o (i s ) v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 1.61 2.46 4.17 7.35 a a a a current limit threshold (i lim ) 27 37.5 a short circuit current(i sc ) rms, hiccup mode, see note 3 v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 8 6 5 4 a a a a ef ciency ( ) 50% of max i o v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 83.6 89 92.8 95.1 % % % % max i o v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 77.4 84.6 90 93.5 % % % % power dissipation at max i o (p d ) v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 4.37 4.54 5.01 5.77 w w w w input idling power (no load)(p li ) default con guration: continues conduction mode, ccm v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 0.56 0.57 0.67 0.92 w w w w
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 13 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter product electrical specification, vertical ( continued ) parameter conditions/description min typ max units input standby power (p ctrl ) turned off with ctrl-pin default con guration: monitoring enabled, precise timing enabled 170 mw internal input capacitance (c i ) 70 f internal output capacitance (c o ) 200 f total external output capacitance (c out ) see note 9 300 15,000 f esr range of capacitors (per single capacitor) (c out ) see note 9 5 30 m load transient peak voltage deviation (l to h/h to l) load step 25-75-25% of max i o (v tr1 ) default con guration di/dt = 2 a/ s c o = 470 f (minimum external capacitance) see note 12 v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 115 122 143 174 mv mv mv mv load transient recovery time note 5 (l to h/h to l) load step 25-75-25% of max i o (t tr1 ) default con guration di/dt = 2 a/ s c o = 470 f (minimum external capacitance) see note 12 v o = 0.6 v v o = 1.0 v v o = 1.8 v v o = 3.3 v 60 65 115 130 s s s s switching frequency (f s ) 320 khz switching frequency range (f s ) pmbus con gurable 200-640 khz switching frequency set-point accuracy (f s ) -5 5 % control circuit pwm duty cycle 5 95 % minimum sync pulse width 150 ns input clock frequency drift tolerance external clock source -13 13 % input under voltage lockout, uvlo uvlo threshold 3.85 v uvlo threshold range pmbus con gurable 3.85-14 v set point accuracy -150 150 mv uvlo hysteresis 0.35 v uvlo hysteresis range pmbus con gurable 0-10.15 v delay 2.5 s fault response see note 3 automatic restart, 70 ms input over voltage protection, iovp iovp threshold 16 v iovp threshold range pmbus con gurable 4.2-16 v set point accuracy -150 150 mv iovp hysteresis 1 v iovp hysteresis range pmbus con gurable 0-11.8 v delay 2.5 s fault response see note 3 automatic restart, 70 ms power good, pg, see note 2 pg threshold 90 %v o pg hysteresis 5 %v o pg delay direct after dlc ms pg delay range pmbus con gurable 0-500 s
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 14 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter product electrical specification, vertical ( continued ) parameter conditions/description min typ max units output voltage over/under voltage protection, ovp/uvp uvp threshold 85 %v o uvp threshold range pmbus con gurable 0-100 %v o uvp hysteresis 5 %v o ovp threshold 115 %v o ovp threshold range pmbus con gurable 100-115 %v o uvp/ovp response time 25 s uvp/ovp response time range pmbus con gurable 5-60 s fault response see note 3 automatic restart, 70 ms over current protection, ocp ocp threshold 32 a ocp threshold range pmbus con gurable 0-32 a protection delay see note 4 32 t sw protection delay range pmbus con gurable 1-32 t sw fault response see note 3 automatic restart, 70 ms over temperature protection, otp at p2 see note 8 otp threshold 120 c otp threshold range pmbus con gurable -40 125 c otp hysteresis 25 c otp hysteresis range pmbus con gurable 0-165 c fault response see note 3 automatic restart, 240 ms logic input low threshold(v il ) sync, sa0, sa1, scl, sda, ddc, ctrl, vset 0.8 v logic input high threshold (v ih )2v logic input low sink current(i il ) ctrl 0.6 ma logic output low signal level (v ol ) sync, scl, sda, salert, ddc, pg 0.4 v logic output high signal level (v oh ) 2.25 v logic output low sink current (i ol ) 4ma logic output high source current (i oh ) 2ma setup time, smbus(t set ) see note 1 300 ns hold time, smbus(t hold ) see note 1 250 ns bus free time, smbus(t free ) see note 1 2 ms internal capacitance on logic pins (c p ) 10 pf initialization time see note 10 40 ms output voltage delay time see note 6 delay duration see note 16 10 ms delay duration range pmbus con gurable 5-500,000 ms delay accuracy turn-on -0.25/+4 ms delay accuracy turn-off -0.25/+4 ms output voltage ramp time see note 13 ramp duration 10 ms ramp duration range pmbus con gurable 0-200 ms ramp time accuracy 100 s current sharing operation 20 %
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 15 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter product electrical specification, vertical ( continued ) parameter conditions/description min typ max units vtrk input bias current v vtrk = 5.5 v 110 200 a vtrk tracking ramp accuracy (v o - v vtrk ) 100% tracking, see note 7 -100 100 mv current sharing operation 2 phases, 100% tracking v o = 1.0 v, 10 ms ramp 100 mv vtrk regulation accuracy (v o - v vtrk ) 100% tracking -1 1 % current sharing operation 100% tracking -2 2 % current difference between products in a current sharing group steady state operation max 2 x read_iout monitoring accuracy ramp-up 2 a number of products in a current sharing group 7 monitoring accuracy read_vin vs v i 3% read_vout vs v o 1% read_iout vs i o i o = 0-20 a, t p1 = 0 to +95 c v i = 4.5-14 v, v o = 1.0 v 1.7 a read_iout vs i o i o = 0-20 a, t p1 = 0 to +95 c v i = 4.5-14 v, v o = 0.6-3.3 v 3 a notes: 1: see section i 2 c/smbus setup and hold times ? de nitions. 2: monitorable over pmbus interface. 3: automatic restart ~70 or 240 ms after fault if the fault is no longer present. continuous restart attempts if the fault reappear after restart. 4: t sw is the switching period. 5: within +/-3% of vo 6: see section soft-start power up. 7: tracking functionality is designed to follow a vtrk signal with slew rate < 2.4 v/ms. for faster vtrk signa ls accuracy will depend on the regulator bandwidth. 8: see section over temperature protection (otp). 9: see section external capacitors. 10: see section initialization procedure. 11: see graph output ripple vs external capacitance and operating information section output ripple and noise. 12: see graph load transient vs. external capacitance and operating information section external capacitors. 13: time for reaching 100% of nominal vout. 14: for vout < 1.0 v accuracy is +/-10 mv. for further deviations see section output voltage adjust using pmbus. 15: accuracy here means deviation from ideal output voltage level given by con gured droop and actual load. includes line, load and temperature variations. 16: for current sharing the output voltage delay time must be recon gured to minimum 15 ms. 17: for steady state operation above 1.05 x 3.3 v, please contact your local cui sales representative.
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 16 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter efficiency vs. output current, v i = 5 v power dissipation vs. output current, v i = 5 v efficiency vs. load current and output voltage: t p1 = +25 c, v i = 5 v, f sw = 320 khz, c o = 470 f/10 m. dissipated power vs. load current and output voltage: t p1 = +25 c, v i = 5 v, f sw = 320 khz, c o = 470 f/10 m. efficiency vs. output current, v i = 12 v power dissipation vs. output current, v i = 12 v efficiency vs. load current and output voltage at t p1 = +25 c, v i =12 v, f sw = 320 khz, c o = 470 f/10 m. dissipated power vs. load current and output voltage: t p1 = +25 c, v i =12 v, f sw = 320 khz, c o = 470 f/10 m. efficiency vs. output current and switching frequency power dissipation vs. output current and switching frequency efficiency vs. load current and switch frequency at t p1 = +25 c, v i = 12 v, v o = 1.0 v, c o = 470 f/10 m. default configuration except changed frequency dissipated power vs. load current and switch frequency at t p1 = +25 c, v i = 12 v, v o = 1.0 v, c o = 470 f/10 m. default configuration except changed frequency 75 80 85 90 95 100 0 5 10 15 20 25 [%] [a] 0.6 v 1.0 v 1.8 v 3.3 v 0 1 2 3 4 5 6 0510152025 [w] [a] 0.6 v 1.0 v 1.8 v 3.3 v 75 80 85 90 95 100 0 5 10 15 20 25 [%] [a] 0.6 v 1.0 v 1.8 v 3.3 v 0 1 2 3 4 5 6 0 5 10 15 20 25 [w] [a] 0.6 v 1.0 v 1.8 v 3.3 v 70 75 80 85 90 95 0 5 10 15 20 25 [%] [ a ] 200 khz 320 khz 480 khz 640 khz 0 1 2 3 4 5 6 0510152025 [w] [ a ] 200 khz 320 khz 480 khz 640 khz typical characteristics, vertical ( continued )
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 17 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter l o a d tr a n s i e n t v s . e x t e r n a l c a p a c i t a nc e , v o = 1 . 0 v l o a d t r ans i e n t v s . e x t e r n a l ca p a c i t a n c e, v o = 3 . 3 v l o a d t r a n s i e n t pe a k v o l t ag e d e v i a t i o n v s . e x t e r n a l cap a c i tanc e . s t e p ( 6 . 25 - 1 8 . 7 5 - 6 . 25 a) . p ar a l l e l cou p l i n g o f c a pac i t o r s w i t h 47 0 f / 1 0 m , t p1 = + 2 5 c . v i = 1 2 v, v o = 1 . 0 v , f s f f w = 3 20 kh z , d i / d t = 2 a / a a s load t r a n s i e n t p e a k vol t a g e d ev i a t i on v s . e x t e rna l c a p acit a n c e . s t ep (6 . 25 - 1 8 . 75 - 6 . 2 5 a) . p a ra l l e l cou p l i ng o f c a p a c i t o r s w i t h 4 7 0 f / 1 0 m , t p 1 = + 25 c . v i = 1 2 v , v o = 3 . 3 v , f s f f w = 3 2 0 k h z , d i / d t = 2 a / s l o a d t r a n sie n t v s . s w i t c h f r equ e n cy l o a d t r a n s i e n t pe a k v o lt ag e d e v i a t i o n v s . f r e q u e n c y . s t e p - c h a n g e ( 6 . 2 5- 18 . 7 5 - 6 . 2 5 a). t p1 = + 2 5 c . v i = 1 2 v, v o = 1 . 0 v , c o = 4 7 0 f / 10 m n o t e : f o r u n i v e r s a l p i d , s ee s e c t i o n d y na m i c l o o p c o m pen s a t i o n ( d l c ). 0 7 0 1 4 0 21 0 28 0 35 0 0123 4 5 [ m v ] [ m f ] u n i v e r s a l p i d , n o n l r d l c , n o n l r u n i v e r s a l p i d , d e f a u l t n lr d l c , d e f a u l t n lr u n i v e r s a l p i d , o pt . nl r d l c , o pt . nl r 0 7 0 1 4 0 21 0 28 0 35 0 01234 5 [ m v ] [m f ] u n i v e r s a l p i d , n o n l r d l c , n o n l r u n i v e r s a l p i d , d e fa u l t n l r d l c , d e fa u l t n l r u n i v e r s a l p i d , o p t . n l r d l c , o p t . n l r 0 7 0 1 4 0 21 0 28 0 35 0 20 0 30 0 4 0 0 50 0 6 0 0 [ m v ] [ k h z ] u n i v e r s a l p i d , n o n l r d l c , n o n l r u n i v e r s a l p i d , d e f a u l t n lr d l c , d e f a u l t n lr u n i v e r s a l p i d , o pt . nl r d l c , o pt . nl r typical characteristics, vertical ( continued )
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 18 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter output current derating, v o = 0.6 v output current derating, v o = 1.0 v a vailable load current vs. ambient air temperature and airflow at v o = 0.6 v, v i = 12 v. see thermal consideration section. available load current vs. ambient air temperature and airflow at v o = 1.0 v, v i = 12 v. see thermal consideration section. output current derating, v o = 1.8 v output current derating, v o = 3.3 v a vailable load current vs. ambient air temperature and airflow at v o = 1.8 v, v i = 12 v. see thermal consideration section. a vailable load current vs. ambient air temperature and airflow at v o = 3.3 v, v i = 12 v. see thermal consideration section. current limit characteristics, v o = 1.0 v current limit characteristics, v o = 3.3 v o utput voltage vs. load current at t p1 = +25 c, v o = 1.0 v. note: output enters hiccup mode at current limit. o utput voltage vs. load current at t p1 = +25 c, v o = 3.3 v. note: output enters hiccup mode at current limit. 0 5 10 15 20 25 30 50 60 70 80 90 100 110 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0 5 10 15 20 25 30 50 60 70 80 90 100 110 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0 5 10 15 20 25 30 30 40 50 60 70 80 90 100 110 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0 5 10 15 20 25 30 30 40 50 60 70 80 90 100 110 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0,0 0,2 0,4 0,6 0,8 1,0 1,2 25 27 29 31 33 35 [v] [a] 4.5 v 5.0 v 12 v 14 v v i = 4.5 v v i = 5.0, 12, 14 v 0,0 1,0 2,0 3,0 4,0 25 27 29 31 33 35 [v] [a] 4.5 v 5.0 v 12 v 14 v v i = 4.5, 5.0 v v i = 12, 14 v typical characteristics, vertical ( continued )
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 19 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter output ripple vs. input voltage output ripple vs. frequency output voltage ripple v pk-pk at: t p1 = +25 c, c o = 470 f/10 m, i o = 25 a. output voltage ripple v pk-pk at: t p1 = +25 c, v i = 12 v , c o = 470 f/10 m, i o = 25 a. default configuration except changed frequency. output ripple vs. external ca pacitance load regulation, v o = 1.0 v output voltage ripple v pk-pk at: t p1 = +25 c, v i = 12 v. i o = 25 a. parallel coupling of capacitors with 470 f/10 m load regulation at v o =1.0 v, t p1 = +25 c, c o = 470 f/10 m 0 10 20 30 40 50 5791113 [mv pk-pk ] [v] 0.6 v 1.0 v 1.8 v 3.3 v 0 20 40 60 80 100 200 300 400 500 600 [mv pk-pk ] [khz] 0.6 v 1.0 v 1.8 v 3.3 v 0 10 20 30 40 50 012345 [mv] [mf] 0.6v 1.0 v 1.8 v 3.3 v 0,990 0,995 1,000 1,005 1,010 0 5 10 15 20 25 [v] [a] 4.5 v 5.0 v 12 v 14 v typical characteristics, vertical ( continued )
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 20 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter start-up by input source shut-down by input source start-up enabled by connecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 25 a top trace: output voltage (0.5 v/div.). bottom trace: input voltage (5 v/div.). time scale: (20 ms/div.). shut-down enabled by disconnecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 25 a top trace: output voltage (0.5 v/div). bottom trace: input voltage (5 v/div.). time scale: (2 ms/div.). start-up by ctrl signal shut-down by ctrl signal start-up by enabling ctrl signal at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 25 a top trace: output voltage (0.5 v/div.). bottom trace: ctrl signal (2 v/div.). time scale: (20 ms/div.). shut-down enabled by disconnecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 25 a top trace: output voltage (0.5 v/div). bottom trace: ctrl signal (2 v/div.). time scale: (2 ms/div.). typical characteristics, vertical ( continued )
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 21 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter efficiency vs. output current and switching frequency efficiency vs. load current and switching frequency at t p1 = +25 c, v i = 12 v, v o = 1.0 v, c o = 470 f/10 m default configuration except changed frequency power dissipation vs. output current and switching frequency dissipated power vs. load current and switching frequency at t p1 = +25 c, v i = 12 v, v o = 1.0 v, c o = 470 f/10 m default configuration except changed frequency output ripple vs. switching frequency output voltage ripple v pk-pk at: t p1 = +25 c, v i = 12 v , c o = 470 f/10 m, i o = 25 a resistive load. default configuration except changed frequency. load transient vs. switching frequency load transient peak voltage deviation vs. frequency. step-change (6.25-18.75-6.25 a). tp1 = +25 c, v i = 12 v, v o =1.0 v, c o = 470 f/10 m load transient vs. decoupling capacitance, v o = 1.0 v load transient peak voltage deviation vs. decoupling capacitance. step (6.25-18.75-6.25 a). parallel coupling of capacitors with 470 f/10 m, t p1 = +25 c. v i = 12 v, v o = 1.0 v, f sw = 320 khz, di/dt = 2 a/s load transient vs. decoupling capacitance, v o = 3.3 v load transient peak voltage deviation vs. decoupling capacitance. step (6.25-18.75-6.25 a). parallel coupling of capacitors with 470 f/10 m, t p1 = +25 c. v i = 12 v, v o = 3.3 v, f sw = 320 khz, di/dt = 2 a/s 70 75 80 85 90 95 0 5 10 15 20 25 [%] [a] 200 khz 320 khz 480 khz 640 khz 0 1 2 3 4 5 6 0 5 10 15 20 25 [w] [a] 200 khz 320 khz 480 khz 640 khz 0 30 60 90 120 150 200 300 400 500 600 [mv pk-pk ] [khz] 0.6 v 1.0 v 1.8 v 3.3 v 0 100 200 300 400 200 300 400 500 600 [mv] [khz] universal pid, no nlr dlc, no nlr universal pid, default nlr dlc, default nlr universal pid, opt. nlr dlc, opt. nlr 0 100 200 300 400 012345 [mv] [mf] universal pid, no nlr dlc, no nlr universal pid, default nlr dlc, default nlr universal pid, opt. nlr dlc, opt. nlr 0 100 200 300 400 012345 [mv] [mf] universal pid, no nlr dlc, no nlr universal pid, default nlr dlc, default nlr universal pid, opt. nlr dlc, opt. nlr typical characteristics
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 22 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter mechanical drawing ( horizontal, surface mount ) units: mm [inches] tolerance unless speci ed: x.x 0.50 [0.02] x.xx 0.25 [0.01] (not applied on footprint or typical values) pin number pin name material plating 1a vin copper alloy min 0.1 m au over 1~3 m ni 2a gnd 3a vout 4a vtrk/pg brass min 0.1 m au over 2 m ni 4b pref 5a +s 5b -s 6a sa0 6b ddc 7a scl 7b sda 8a vset 8b sync 9a salrt 9b ctrl
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 23 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter mechanical drawing ( horizontal, through hole mount ) units: mm [inches] tolerance unless speci ed: x.x 0.50 [0.02] x.xx 0.25 [0.01] (not applied on footprint or typical values) pin number pin name material plating 1a vin copper alloy min 8~13 m matte tin over 2.5~5 m ni 2a gnd 3a vout 4a vtrk/pg brass min 0.2 m au over 1.27 m ni 4b pref 5a +s 5b -s 6a sa0 6b ddc 7a scl 7b sda 8a vset 8b sync 9a salrt 9b ctrl
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 24 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter mechanical drawing ( vertical, through hole mount ) pin number pin name material plating 1a vin copper alloy min 0.1 m au over 1~3 m ni 2a gnd 3a vout 4a +s min 0.1 m au over 1 m ni 4b -s 5a vset 5b vtrk 6a salrt 6b sda 7a scl 7b sa1 8a sa0 8b sync 9a pg 9b ctrl 10a ddc 10b pref units: mm [inches] tolerance unless speci ed: x.x 0.50 [0.02] x.xx 0.25 [0.01] (not applied on footprint or typical values)
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 25 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter operating information the ndm2z-25 modules are available in different con gurations; not all pins and functions are supported by each con guration. this document describes all pins and functions. the novum z products pmbus commands application note de nes the available pmbus? commands. required configurations ndm2z-25 module pins each ndm2z-25 module should have a resistor placed between vset and pref to set the output voltage of the module. the maximum output voltage which can be con gured by pmbus commands can never exceed 110% of the voltage set by the vset pin. the smbus address of each module is set by either pin-strap con guration or resistor value associated with the sa0 and sa1 pins. more informa- tion regarding setting the smbus address for a module can be found in the section titled ?smbus?. pcb layout good performance of any point of load voltage regulator module can only be achieved with careful pcb layout considerations. ground planes or very wide traces should be used for power and ground routing. input capacitors should be placed close to the input voltage pins of the module and output capacitors should be placed close to the load. the module should also be placed as close as possible to the load. input and output capacitors input capacitors input capacitors are recommended to be used with the ndm2z-25 module in order to minimize input voltage ripple. a 330 f poscap or electrolytic and 3x 22 f ceramic capacitors should be placed as close as possible to the input pins of the module. additional input capacitors may be used if less input voltage ripple is desired. output capacitors output capacitors are recommended to be used with the ndm2z-25 module in order to improve transient response and minimize output voltage ripple. a 330 f poscap or electrolytic and 3x 22 f ceramic capacitors should be placed as close as possible to the load. additional output capacitors may be used to further improve the output voltage characteristics. power conversion and management power conversion overview the ndm2z-25 module has several features to enable high power conversion efficiency. non-linear loop response (nlr) improves the response time and reduces the output deviation as a result of load transients. the incorporation of dfm enhances the performance of cui modules over that available from conventional analog pol offerings. power management overview the ndm2z-25 module incorporates a wide range of power management features. all power management functions can be configured via the smbus interface. the ndm2z-25 can monitor and report many characteristics of the module including input voltage, output voltage, output current and internal temperature. additionally, the ndm2z-25 includes circuit protection features that protect the module and load from damage due to system faults. monitoring parameters can also be configured to provide alerts for specific conditions. the ability of cui modules to digitally control, configure and monitor os features provides significant benefits over traditional analog pol products. configuring the module pin settings pins sa0 and sa1 are used to set the smbus address of the ndm2z-25 module. details of this feature are discussed in the section titled ?smbus?. pin sync is used to synchro- nize the switching clock of the module to an external clock source. more information regarding synchronization can be found in the section titled ?switching frequency and synchronization?. pin vset is used to configure the output voltage of the module. the voltage established by the vset pin limits the maximum output voltage that can be configured by smbus commands. the sa0, sa1, sync and vset pin configurations are read by the module when power is applied or whenever a smbus restore command is issued. the ctrl pin is active high and can be used to enable the module. internal connections on the module will drive the ctrl pin high if it is left floating. pins +s and -s are used for remote voltage sensing of the output voltage.
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 26 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter soft-start delay ramp times once ctrl is asserted the ndm2z-25 module requires a pre-ramp delay time before the output voltage may be allowed to start the ramp-up process. after the delay period has expired, the output will begin to ramp towards the target voltage according to the pre-con gured soft-start ramp time that has been set. it is recommended to set the soft-start ramp time to a value greater than 500 s in order to prevent fault conditions due to excessive inrush current. soft start delay and ramp times may be set using pmbus commands. output pre-bias an output pre-bias condition exists when a non-zero voltage is present on the ndm2z-25 module output before the module output voltage is enabled. if a pre-bias voltage exists, the output voltage of the module is set to match the existing pre-bias voltage. the output voltage is then ramped to the final regulation value in the specified ramp time. the pre-bias voltage can be higher or lower than the final output voltage. higher pre-bias output voltages will cause energy to be pumped into the input voltage rail powering the module. this condition could cause the module to report an error condition if the input voltage exceeds the input over voltage lock out threshold. the module will report an error condition if the pre-bias output voltage exceeds the output over voltage protection threshold. unused pins table 1 describes the required or allowed connections for unused pins on the ndm2z-25 module. table 1: unused pins con guration of parameters using the smbus the ndm2z-25 module is supplied with default settings. all module settings (except for module smbus address, con gured by pins sa0 and sa1) can be re-con gured via the smbus interface. the output voltage can not be set to greater than 110% of the voltage set by the vset pin. start-up procedure start-up sequence the ndm2z-25 module follows an internal start-up procedure after power is applied to pin vin. table 2 describes the start-up sequence. if the module is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting ctrl (or applying input voltage to the module if ctrl is not used). once this process is completed, the module is ready to accept assertion of ctrl and commands via the smbus interface. table 2: ndm2z-25 start-up sequence vset tie to pref with 133 k resistor, see vout_command pmbus command vtrk, sa0, sa1, sync, ctrl, +s, -s float ddc, scl, sda, salrt pulled high with resistor, see "recommended operatin conditions" step step name description time duration 1 power applied or restore_factory input voltage is applied to ndm2z-25 module pin vin or restore_factory pmbus command issued depends on input supply ramp time 2 factory con guration settings module loads factory con guration settings. this step is also performed after using pmbus commands to restore the factory con guration le. approximately 10 ms (module will ignore a ctrl signal and pmbus commands during this period) 3 sa0, sa1, sync and vset pin settings module loads values con gured by the sa0, sa1, sync and vset pins. 4 default con guration settings module loads default con guration settings. this data over-rides pin setting data, except for maximum limit for vout_command. this step also performed after using pmbus commands to restore the default con guration le. 5 user con guration settings module loads user con guration settings. this data over-rides pin setting and default con guration data, except for maximum limit for vout_command. this step also performed after using pmbus commands to restore the user con guration le. 6 module ready the module is ready to accept a ctrl signal. --- 7 pre-ramp delay the module requires approximately 5 ms following a ctrl signal and prior to ramping its output. additional pre-ramp delay may be con gured using pmbus commands. approximately 5 ms
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 27 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter power good the pg pin on the ndm2z-25 module will assert if the output of the module is within tolerance of the target voltage and no fault conditions exist. a pg delay period is de ned as the time from when all conditions within the module for asserting pg are met to when pg is actually asserted. by default, pg delay is set equal to the soft-start ramp time setting. the tolerance, polarity and delay of pg may be con gured via pmbus commands. soft-stop delay and ramp times after ctrl is de-asserted the ndm2z-25 module utilizes a pre-ramp delay time before the output starts the ramp- down process. after the delay period has expired, the output will begin to ramp towards ground according to the pre-con gured soft-stop ramp time that has been set. it is recommended to set the soft-start ramp down to a value greater than 500 s in order to prevent voltage spikes in the module input supply rail due the energy stored in the output capacitors. there will be a delay after the output voltage has reached ground potential and then the output of the module will be set to high impedance. once the output of the module is high impedance the output voltage may oat to a non-zero value if another source or leakage path is connected to the output. the soft-stop delay and ramp times may be con gured via pmbus commands. pmbus commands can be used to set the output of the ndm2z-25 module to high impedance as soon as the output voltage drops below a selectable threshold. output voltage setting pin-strap and resistor setting methods using the pin-strap method, the voltage on the vout pin of the ndm2z-25 module can be set to one of three default voltages as shown in table 3. table 4 lists the available output voltage settings with a resistor connected between vset and pref. table 3: pin-strap vout voltage settings table 4: resistor vout voltage settings smbus setting method the voltage present at the vout pin of the ndm2z-25 module can be reconfigured using pmbus commands. a voltage level reconfigured by a pmbus command over- rides the voltage set by the vset pin, but cannot be set to greater than 110% of the voltage set by the vset pin. voltage tracking the ndm2z-25 module includes a feature that allows the output ramp voltage to track the ramp of a reference voltage which is applied to the vtrk pin. the voltage ramp tracking capability can be configured so that member modules track at either 50% or 100% of the reference voltage ramp rate. in addition, a member module can be configured so that the termination voltage either tracks or ignores perturbations on the reference voltage once it has stabilized. tracking at 50% and tracking final voltage perturbations is intended for ddr memory applications. all other applications which required voltage tracking should use 100% tracking and ignore final voltage perturbations. the reference voltage for tracking must have a target volt- age which is equal to or greater than the target voltage of the member modules. the turn-on delay of the reference voltage must be at least 10 ms greater than that set for the member modules. in voltage tracking mode, the turn-off delay of the member modules establishes the time duration which the member modules will track the reference voltage after ctrl is de-asserted. the turn-off delay of the member modules must be at least 5 ms greater than the sum of the turn-off delay and fall time of the reference voltage. vset vout (v) low (< 0.8 v) 0.6 open (n/c) 1.2 high (> 2.0 v) 2.5 resistor (k ) vout (v) resistor (k ) vout (v) 10.0 0.60 38.3 1.30 11.0 0.65 42.2 1.40 12.1 0.70 46.4 1.50 13.3 0.75 51.1 1.60 14.7 0.80 56.2 1.70 16.2 0.85 61.9 1.80 17.8 0.90 68.1 1.90 19.6 0.95 75.0 2.00 21.5 1.00 82.5 2.10 23.7 1.05 90.9 2.20 26.1 1.10 100.0 2.30 28.7 1.15 110.0 2.50 31.6 1.20 121.0 3.00 34.8 1.25 133.0 3.30
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 28 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter current sharing modules which are also configured to track a voltage must have all of the vtrk pins tied together. all of the ctrl pins of the member modules must also be connected together and driven by a common source. the rise and fall times of the member modules should be set between 5 ms and 10 ms to ensure current sharing while ramping. pmbus commands can be used to configure the voltage tracking features. voltage margining the ndm2z-25 module offers a means to vary the output voltage higher or lower relative to the nominal voltage setting. the rate of change of the output voltage during voltage margining is also configurable. the margin feature can be reconfigured through pmbus commands. switching frequency and synchronization switching frequency the switching frequency of the ndm2z-25 module can be recon gured by pmbus commands or controlled by an external clock source connected to the sync pin. if the module is operated at a switching frequency of other than the factory default setting, the compensation may need to be adjusted and the ripple, noise, transient response and ef ciency may be affected. sync auto detect the ndm2z-25 module will automatically check for a clock signal on the sync pin after ctrl is asserted (or applying input voltage to the module if ctrl is not used). if a clock signal is present, the module will synchronize to the rising edge of the external clock. the external clock signal must be stable and conform to the ?recommended operating conditions? parameters when ctrl is asserted (or applying input voltage to the module if ctrl is not used). in the event of a loss of the external clock signal, the output voltage of the module may show transient overshoot or undershoot and the module will automatically con gure to switch at a frequency close to the previous incoming frequency. if no incoming clock signal is present when ctrl is asserted (or applying input voltage to the module if ctrl is not used), the module will switch at the frequency set by the con guration le. control loop adaptive loop compensation the ndm2z-25 module employs automatic adaptive loop compensation to increase the performance and stability of the module over a wide range of conditions. the default setting con gures the module to re-compensate the control loop every time the output voltage ramps to the regulated level. pmbus commands can be used to con gure when the module re-compensates the loop. the user also has the option to manually con gure the loop compensation. non-linear response (nlr) settings the ndm2z-25 module incorporates a non-linear response (nlr) loop that decreases the response time and the output voltage deviation in the event of a sudden output load current step. this implementation results in a higher equivalent loop bandwidth than what would be possible using a traditional linear loop. pmbus commands can be used to con gure the nlr response of the module. adaptive diode emulation please contact cui technical support regarding the implementation of adaptive diode emulation. adaptive frequency control the ndm2z-25 module includes adaptive frequency control to improve conversion ef ciency. adaptive frequency control is not available for current sharing groups and is not allowed when the module is placed in auto-detect mode and a clock source is present on the sync pin. adaptive frequency control is only available while the module is operating within adaptive diode emulation mode. adaptive frequency control can be enabled and disabled with pmbus commands. multi-module configuration output sequencing multiple device sequencing of ndm2z-25 modules may be achieved by issuing pmbus commands to assign the preceding device in the sequencing chain as well as the device that will follow in the sequencing chain. the ctrl pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. ctrl must be driven low to initiate a sequenced turnoff of the group.
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 29 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter fault spreading ndm2z-25 modules can be configured to broadcast a fault event over the ddc (group communication bus) to the other modules in the group. when a nondestructive fault occurs and the module is configured to shut down on a fault, the module will shut down and broadcast the fault event over the ddc. the other modules on the ddc will shut down together if configured to do so, and will attempt to re-start in their prescribed order if configured to do so. pmbus commands can be used to confi gure the transmission and reception of faults. active current sharing paralleling multiple ndm2z-25 modules can be used to increase the output current capability of a single power rail. by connecting the ddc of each module together and con guring the modules as a current sharing rail, the units will share the load current. upon system start-up, the module with the lowest member position as selected with the pmbus command is de ned as the reference module; the remaining modules are members. the reference module broadcasts the current over the ddc. the output voltages of the member modules are controlled by the reference current information to balance the current loading of each module in the system. a current sharing rail can be part of a system sequencing group. for fault con guration, the current share rail is con gured in a quasi-redundant mode. in this mode, when a member module fails the remaining members will continue to operate and attempt to maintain regulation. if fault spreading is enabled, the current share rail failure is broadcast only after the entire current share rail fails. members of the current sharing rail can be disabled to improve system power conversion ef ciency. if the reference module fails or is disabled then the remaining module with the lowest member position will become the new reference module. a change to the number of members of a current sharing rail will cause automatic phase re-distribution of the members of that current sharing rail. if the members of a current sharing rail are forced to shut down due to an observed fault, all members of the rail will attempt to re-start simultaneously after the fault has cleared. pmbus commands can be used to con gure current sharing. phase spreading when multiple ndm2z-25 modules share a common dc input supply, it may be desirable to adjust the clock phase offset of each module. in order to enable phase spreading, all modules must be synchronized to the same switching clock. for modules driven by a common synchronizing clock the phase offset of each module is controlled by the module addresses; phase offset = device address x 45. for example: ? a module address of 0x00 or 0x20 would con gure 0 of phase offset ? a module address of 0x01 or 0x21 would con gure 45 of phase offset ? a module address of 0x02 or 0x22 would con gure 90 of phase offset the phase offset of each module may also be set via the pmbus. power fault management input under and over voltage lockout input under voltage lockout (uvlo) and input over voltage lockout (ovlo) indicate faults for the ndm2z-25 module when the input voltage falls outside of preset thresholds. the default response due to an input voltage fault is an immediate shutdown of the module. the module will continuously check for the presence of the fault condition. once the fault condition is no longer present, the module will be re-enabled. pmbus commands can be used to con gure the thresholds and response of the module to the fault condition. output under and over voltage protection the ndm2z-25 module employs an output voltage protection circuit that can be used to protect load circuitry from being subjected to voltages outside of prescribed limits. a hardware comparator is used to compare the voltage seen at the +s pin to voltage thresholds. if the +s pin voltage is outside of these thresholds the pg pin will de-assert and the module will indicate a fault condition.
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 30 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter the default response to an output voltage fault is to immediately shut down. the module will continuously check for the presence of the fault condition, when the fault condition no longer exists the module will be re-enabled. pmbus commands can be used to set the voltage thresholds and con gure the response of the module to the fault condition. when operating from an external clock the only allowed response to an output voltage fault is an immediate shutdown. output over current protection output over current protection will protect the ndm2z-25 module and load from damage if an overload condition is imposed on the output. the module will indicate a fault condition when the output current limit threshold is exceeded. the default response from an output current fault is an immediate shutdown of the module. the module will continuously check for the presence of the fault condition, and if the fault condition no longer exists the module will be re-enabled. pmbus commands can be used to con gure the current limit threshold and the response of the module to the fault condition. thermal overload protection the ndm2z-25 module includes a thermal sensor that measures the temperature of the module and indicates a fault when the temperature exceeds a preset limit. the default response from a temperature fault is an immediate shutdown of the module. the module will continuously check for the fault condition and once the fault has cleared the module will be re-enabled. pmbus commands can be used to con gure the thermal protection threshold and the response of the module to the fault condition. permanent damage to the module may result if the thermal limit is set too high. smbus smbus communications the ndm2z-25 module provides a smbus interface that enables the user to con gure the module operation as well as monitor input and output parameters. the module can be used with any standard 2-wire i 2 c host device, accepts most standard pmbus commands, is compatible with smbus version 2.0 and includes an salrt line to help mitigate bandwidth limitations related to continuous fault monitoring. it is recommended that ctrl be pulled low while con guring the module with pmbus commands. pull-up resistors are required on the smbus lines as described in "recommended operating conditions". smbus addresses when communicating with multiple smbus devices using the smbus interface, each device must have a unique address so the host can distinguish between the devices. the ndm2z-25 module address can be set according to the pin-strap options listed in table 5; address values are right-justi ed. if additional module addresses are required, a resistor can be connected to pin sa0 as shown in table 6 to provide up to 25 unique module addresses. table 5: pin-strap smbus addressing table 6: single resistor smbus addressing when using only pin sa0 to set the smbus address, pin sa1 should be tied to pref. if more than 25 unique module addresses are required or if other smbus address values are desired, pins sa0 and sa1 can be con gured with a resistor to pref as listed in table 7. using this method, the user can theoretically con gure up to 625 unique smbus addresses. however, the smbus is inherently limited to 128 modules so attempting to con gure an address higher than 128 (0x80) will cause the module address to repeat (i.e, attempting to con gure a module address of 129 (0x81) would result in a module address of 1). therefore, the user should use index values 0-4 on pin sa1 and the full range of index values on pin sa0, which will provide 125 module address combinations. sa0 address high 0x25 open 0x24 low 0x23 r sa0 (k ) address r sa0 (k ) address 10.0 0x4b 34.8 0x58 11.0 0x4c 38.3 0x59 12.1 0x4d 42.2 0x5a 13.3 0x4e 46.4 0x5b 14.7 0x4f 51.1 0x5c 16.2 0x50 56.2 0x5d 17.8 0x51 61.9 0x5e 19.6 0x52 68.1 0x5f 21.5 0x53 75.0 0x60 23.7 0x54 82.5 0x61 26.1 0x55 90.9 0x62 28.7 0x56 100.0 0x63 31.6 0x57
for more information, please visit the product page. ?????????????????? cui .com date 12/21/2015 page 31 of 32 cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter note that the smbus address 0x4b is reserved for module test and cannot be used in the system. table 7: dual resistor smbus addressing monitoring via smbus a system controller can be used to monitor the ndm2z-25 module system parameters through the smbus. fault conditions can be detected by monitoring the salrt pin, which will be asserted when pre-con gured fault conditions occur. modules can also be monitored for power conversion parameters including but not limited to the following: ? input voltage ? output voltage ? output current ? module temperature ? switching frequency ? duty cycle single wire communications digital-dc bus the ddc (digital-dc communication bus) is used to communicate between ndm2z modules. this dedicated bus provides the communication channel between modules for features such as sequencing, fault spreading, and current sharing. a pull-up resistor is required on the ddc as de ned in ?recommended operating conditions?. snapshot ? parameter capture the ndm2z-25 module offers features that enable the user to capture parametric data during normal operation or following a fault. the snapshot feature enables the user to read status and parameter values via a block read transfer through the smbus. this can be done during normal operation, although it should be noted that reading the 22 bytes will occupy the smbus for up to 1400 s. the snapshot_control command enables the user to store the snapshot parameters to ash memory in response to a pending fault as well as to read the stored data from ash memory after a fault has occurred. automatic writes to ash memory following a fault are triggered when any fault threshold level is exceeded, provided that the speci c response to that fault is to shut down (writing to ash memory is not allowed if the module is con gured to re-try following the speci c fault condition). it should also be noted that the input voltage to the module must be maintained during the time when the module is writing the data to ash memory; a process that requires between 700 s to 1400 s depending on whether the data is set up for a block write. undesirable results may be observed if the input voltage to the module drops too low during this process. in the event that the module experiences a fault and power is lost, the user can extract the last snapshot parameters stored during the fault by using the smbus to transfer data from ash memory to ram and then using the smbus to read data from ram. thermal considerations mounting heat from the ndm2z-25 module will be conducted through the pins to the host board. provisions must be made for the host board to accommodate this additional heating. air ow air ow past the ndm2z-25 module will assist in cooling the module. factors affecting the ef ciency of the cooling include the rate, direction and temperature of the air ow. 10.0 11.0 12.1 13.3 14.7 r sa1 (k ) 10.0 0x00 0x19 0x32 0x4b 0x64 11.0 0x01 0x1a 0x33 0x4c 0x65 12.1 0x02 0x1b 0x34 0x4d 0x66 13.3 0x03 0x1c 0x35 0x4e 0x67 14.7 0x04 0x1d 0x36 0x4f 0x68 16.2 0x05 0x1e 0x37 0x50 0x69 17.8 0x06 0x1f 0x38 0x51 0x6a 19.6 0x07 0x20 0x39 0x52 0x6b 21.5 0x08 0x21 0x3a 0x53 0x6c 23.7 0x09 0x22 0x3b 0x54 0x6d 26.1 0x0a 0x23 0x3c 0x55 0x6e 28.7 0x0b 0x24 0x3d 0x56 0x6f 31.6 0x0c 0x25 0x3e 0x57 0x70 34.8 0x0d 0x26 0x3f 0x58 0x71 38.3 0x0e 0x27 0x40 0x59 0x72 42.2 0x0f 0x28 0x41 0x5a 0x73 46.4 0x10 0x29 0x42 0x5b 0x74 51.1 0x11 0x2a 0x43 0x5c 0x75 56.2 0x12 0x2b 0x44 0x5d 0x76 61.9 0x13 0x2c 0x45 0x5e 0x77 68.1 0x14 0x2d 0x46 0x5f 0x78 75.0 0x15 0x2e 0x47 0x60 0x79 82.5 0x16 0x2f 0x48 0x61 0x7a 90.9 0x17 0x30 0x49 0x62 0x7b 100.0 0x18 0x31 0x4a 0x63 0x7c r sa0 (k )
for more information, please visit the product page. ????????? cui inc series: ndm2z-25 description: auto compensated, digital dc-dc pol converter date 12/21/2015 page 32 of 32 novum and architects of modern power are trademarks of cui. pmbus is a trademark of smif, inc. auto-control is a trademark of powervation ltd. all other trademarks are the property of their respective owners. cui offers a two (2) year limited warranty. complete warranty information is listed on our website. cui reserves the right to make changes to the product at any time without notice. information provided by cui is believed to b e accurate and reliable. however, no responsibility is assumed by cui for its use, nor for any infringements of patents or other rights of third parties which may result from its use . cui products are not authorized or warranted for use as critical components in equipment that requires an extremely high level of reliability. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support devi ce or system, or to affect its safety or effectiveness. headquarters 20050 sw 112th ave. tualatin, or 97062 800.275.4899 fax 503.612.2383 cui .com techsupport@cui.com rev. date 1.0 09/28/2015 1.1 12/14/2015 1.2 12/21/2015 the revision history provided is for informational purposes only and is believed to be accurate. revision history

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